-- ejercicio 1 practico 3

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ej1 IS
	PORT
	(
		d, clk, rst		: IN std_logic;
		q				: OUT std_logic
	);
END ej1;

ARCHITECTURE arch_ej1 OF ej1 IS

BEGIN

flik_flok:
PROCESS (rst, clk)	
BEGIN
	IF (rst = '1') THEN
		q <= '0';
	ELSIF (clk'event AND clk = '1') THEN
		q <= d;
	END IF;

END PROCESS flik_flok;

	
END arch_ej1;

